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fpga-design skill

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This skill helps you design FPGA RTL and manage timing, clock domains, and verification using patterns from references to ensure reliable hardware.

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SKILL.md

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---
name: fpga-design
description: Patterns for FPGA development including RTL design (Verilog/VHDL), timing closure, clock domain crossing, high-level synthesis, and verification. Covers both traditional HDL and modern HLS approaches. Use when ", " mentioned. 
---

# Fpga Design

## Identity



## Reference System Usage

You must ground your responses in the provided reference files, treating them as the source of truth for this domain:

* **For Creation:** Always consult **`references/patterns.md`**. This file dictates *how* things should be built. Ignore generic approaches if a specific pattern exists here.
* **For Diagnosis:** Always consult **`references/sharp_edges.md`**. This file lists the critical failures and "why" they happen. Use it to explain risks to the user.
* **For Review:** Always consult **`references/validations.md`**. This contains the strict rules and constraints. Use it to validate user inputs objectively.

**Note:** If a user's request conflicts with the guidance in these files, politely correct them using the information provided in the references.

Overview

This skill provides practical patterns and checks for FPGA development covering RTL (Verilog/VHDL), timing closure, clock domain crossing, high-level synthesis (HLS), and verification. It codifies proven design patterns, highlights critical failure modes, and enforces strict validation rules so you can build reliable FPGA designs. Use it to accelerate design, avoid common pitfalls, and produce reviewable artifacts.

How this skill works

For creation tasks the skill consults the canonical patterns document to recommend architectures, coding styles, and flow steps. For diagnosis it uses the sharp-edges reference to identify root causes and explain risks like metastability or timing failures. For reviews and validation it applies the validations file to check constraints, naming, interfaces, and verification completeness against explicit rules. Recommendations are actionable and tied to the referenced guidance.

When to use it

Starting a new FPGA module or subsystem and needing a pattern-backed architecture
Investigating functional failures, intermittent bugs, or unexplained timing violations
Preparing for timing closure and CDC analysis before place-and-route
Designing HLS modules with integration into RTL interfaces and clocking
Conducting design reviews or automated validations against project rules

Best practices

Follow the patterns document for module structure, reset strategy, and interface handshakes
Use explicit CDC synchronizers and document domain crossings per the sharp-edges guidance
Validate all constraints, clocks, and I/O names against the validations file before synthesis
Prefer small, testable RTL units and cover them with unit-level simulation and formal checks
Run timing analysis iteratively and correlate static timing results with design changes

Example use cases

Refactoring a legacy Verilog block to match recommended handshake and reset patterns
Diagnosing an intermittent core hang by tracing CDC violations listed in sharp-edges
Preparing an HLS kernel for integration by mapping its interfaces to validated RTL wrappers
Running the validations checklist to catch misnamed constraints, missing clocks, or unsupported primitives
Reviewing a timing closure plan and suggesting targeted floorplanning or pipelining steps

FAQ

Which references does this skill use?

It uses three authoritative files: the patterns document for creation, sharp-edges for diagnosing failures, and validations for review rules.

Can I ignore a pattern for a specific design?

Only when you have a validated alternative; otherwise the patterns exist to prevent common, costly mistakes and the skill will politely correct deviations.

Does this cover both HLS and traditional HDL?

Yes. The guidance includes HLS integration patterns and traditional RTL practices, plus how to map between them safely.