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home / skills / a5c-ai / babysitter / ip-core-management

ip-core-management skill

/plugins/babysitter/skills/babysit/process/specializations/fpga-programming/skills/ip-core-management

This skill helps configure and integrate vendor IP cores for FPGA designs, ensuring reproducible, well-documented, and upgrade-safe IP usage.

npx playbooks add skill a5c-ai/babysitter --skill ip-core-management

Review the files below or copy the command above to add this skill to your agents.

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SKILL.md
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---
name: ip-core-management
description: Vendor IP core configuration and integration expertise for FPGA designs
allowed-tools:
  - Read
  - Write
  - Edit
  - Glob
  - Grep
  - Bash
---

# IP Core Management Skill

## Overview

Expert skill for vendor IP core configuration and integration, enabling efficient use of pre-built intellectual property in FPGA designs.

## Capabilities

- Configure Xilinx/AMD IP cores
- Configure Intel/Altera IP cores
- Generate IP output products
- Connect IP interfaces correctly
- Handle IP versioning and updates
- Configure IP parameters via TCL
- Integrate third-party IP cores
- Document IP configurations

## Target Processes

- ip-core-integration.js
- clock-network-design.js
- memory-interface-design.js
- axi-interface-design.js

## Usage Guidelines

### Xilinx IP Configuration
- Use IP Integrator for block design
- Configure via GUI or TCL scripts
- Generate output products before synthesis
- Lock IP versions for reproducibility
- Use IP upgrade advisor for version changes

### Intel IP Configuration
- Use Platform Designer (Qsys)
- Configure system interconnect
- Generate HDL and synthesis files
- Handle parameterization correctly
- Use IP upgrade reports

### Common IP Categories
- **Clock Management**: MMCM, PLL configurations
- **Memory Controllers**: DDR, HBM, QDR
- **Interconnect**: AXI Interconnect, SmartConnect
- **Processing**: MicroBlaze, Nios II
- **Communication**: Ethernet, PCIe, UART

### TCL Scripting
```tcl
create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_0
set_property CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 200 [get_ips clk_wiz_0]
generate_target all [get_ips clk_wiz_0]
```

### Integration Best Practices
- Create wrapper modules for IP
- Document configuration choices
- Version control IP TCL scripts
- Test IP in isolation before integration
- Plan for IP core updates

## Dependencies

- Vendor IP catalog access
- Vendor tool CLI knowledge
- IP licensing understanding

Overview

This skill provides vendor IP core configuration and integration expertise for FPGA designs. It guides setup and parameterization for Xilinx/AMD and Intel/Altera IP, generates output products, and helps manage versioning and updates. The goal is reproducible, automatable integration of pre-built IP into complex FPGA flows.

How this skill works

The skill inspects IP catalogs, vendor tool commands, and TCL scripts to configure cores and generate HDL/synthesis outputs. It maps and connects IP interfaces (AXI, clocks, memory) and produces wrapper modules and documentation for reproducible integration. It also recommends upgrade and version-lock strategies and validates isolated IP behavior before system integration.

When to use it

  • When adding vendor IP cores (clocks, memory, PCIe, Ethernet) to an FPGA project
  • During board bring-up to validate memory controllers and clock networks
  • When automating IP generation via TCL or CI pipelines
  • Before synthesis to generate IP output products and lock versions
  • When updating vendor tools or IP versions and you need a controlled upgrade path

Best practices

  • Use vendor block-design tools (IP Integrator, Platform Designer) for topology and automation
  • Generate IP output products and commit TCL scripts to version control for reproducibility
  • Create lightweight wrapper modules to isolate vendor IP from system logic and simplify testing
  • Validate each IP in isolation (simulation or hardware smoke test) before full integration
  • Lock IP versions and run upgrade advisors when changing toolchains or IP revisions

Example use cases

  • Configure Xilinx clocking resources (MMCM/PLL) via TCL and integrate with AXI-based subsystems
  • Generate and validate DDR/HBM memory controller outputs and timing constraints for a new board
  • Automate Intel Qsys/Platform Designer IP generation in a CI pipeline to produce deterministic builds
  • Integrate a third-party PCIe core, create wrappers, and document configuration choices for handoff
  • Handle IP version migration: run upgrade reports, test in isolation, and apply controlled updates

FAQ

Do I need vendor tools installed to use the skill?

Yes. Access to vendor toolchains or their CLIs is required to generate IP output products and run upgrade checks.

How do you ensure reproducible IP builds?

By scripting IP creation with TCL, locking IP and tool versions, committing TCL to version control, and generating output products before synthesis.