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cdc-analysis skill

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This skill analyzes clock domain crossings and guides synchronizer design to ensure metastability-safe multi-clock FPGA implementations.

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SKILL.md
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---
name: cdc-analysis
description: Specialized skill for clock domain crossing analysis and synchronizer design in FPGA designs
allowed-tools:
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---

# CDC Analysis Skill

## Overview

Expert skill for Clock Domain Crossing (CDC) analysis and synchronizer design, ensuring metastability-safe multi-clock FPGA designs.

## Capabilities

- Identify all clock domain crossings in RTL
- Design 2FF and 3FF synchronizers with ASYNC_REG
- Implement Gray code counters for async FIFOs
- Design handshake protocols (req-ack, valid-ready)
- Calculate MTBF for synchronizers
- Generate CDC constraints (set_false_path, set_max_delay)
- Detect CDC violations (reconvergence, data stability)
- Support Xilinx CDC-aware design flows

## Target Processes

- cdc-design.js
- reset-strategy.js
- clock-network-design.js
- timing-constraints.js

## Usage Guidelines

### Synchronizer Types
- **2FF Synchronizer**: Standard single-bit synchronization (MTBF > 100 years typical)
- **3FF Synchronizer**: High-reliability applications
- **Pulse Synchronizer**: Edge detection across domains
- **Handshake Synchronizer**: Multi-bit data with control signals

### FIFO Design
- Use Gray code for pointer crossing
- Ensure proper empty/full flag generation
- Consider almost-empty/almost-full for flow control
- Apply correct FIFO depth calculation

### Constraint Guidelines
- `set_false_path` for 2FF synchronizer paths
- `set_max_delay` for data bus with valid synchronization
- `set_clock_groups` for asynchronous clocks
- Apply ASYNC_REG attribute to synchronizer flip-flops

### CDC Violations to Detect
- Combinational logic between synchronizer stages
- Fan-out from unsynchronized signals
- Reconvergence of synchronized signals
- Data stability violations

## Dependencies

- CDC analysis tool integration
- Vendor-specific CDC rule knowledge
- Metastability theory understanding

Overview

This skill specializes in Clock Domain Crossing (CDC) analysis and synchronizer design for FPGA projects. It helps identify CDC points, design robust synchronizers and FIFOs, and produce CDC-aware timing constraints to reduce metastability and data corruption risks. It targets practical improvements in multi-clock RTL and supports vendor-aware CDC flows.

How this skill works

The skill scans RTL to locate clock domain boundaries and flags crossings that need synchronization. It suggests and generates 2FF/3FF synchronizers, pulse and handshake schemes, Gray-coded FIFO pointers, and CDC constraints like set_false_path and set_max_delay. It also evaluates common CDC violations (reconvergence, data stability, unsynchronized fan-out) and can estimate synchronizer MTBF for reliability trade-offs.

When to use it

  • During RTL review to find all clock domain crossings
  • When designing multi-clock FIFOs or inter-domain control paths
  • Before synthesis/place-and-route to add CDC constraints
  • When migrating designs between vendor flows (e.g., Xilinx)
  • To validate reset and clock network strategies for metastability risk

Best practices

  • Use 2FF synchronizers for single-bit control; 3FF where higher MTBF is required
  • Mark synchronizer flip-flops with ASYNC_REG vendor attributes
  • Use Gray code for pointer transfer in async FIFOs and verify empty/full logic
  • Avoid combinational logic between synchronization stages and minimize reconvergent paths
  • Add set_false_path/set_clock_groups and set_max_delay constraints to reflect asynchronous relationships

Example use cases

  • Automatically enumerate and report all CDCs in a large SoC RTL codebase
  • Design a pulse or handshake synchronizer for single-event control signals crossing clocks
  • Create Gray-coded async FIFO with correct empty/full flags and almost-empty/full thresholds
  • Generate CDC constraints for a Xilinx flow and annotate synchronizer registers with ASYNC_REG
  • Estimate MTBF for a proposed 2FF vs 3FF synchronizer trade-off

FAQ

When should I use 3FF instead of 2FF synchronizers?

Use 3FF when target MTBF requirements are extremely high or when failure consequences are severe; 2FF is typically adequate for many control signals with MTBF often exceeding practical lifetimes.

How do I handle multi-bit data transfers across clocks?

Prefer handshake synchronizers or asynchronous FIFOs with Gray-coded pointers; never synchronize multi-bit buses with simple flop chains as bit skew creates corruption.