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axi-protocol skill

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This skill helps you implement and verify AMBA AXI protocols in FPGA designs, optimizing throughput and correctness across AXI4, AXI4-Lite, and AXI4-Stream.

npx playbooks add skill a5c-ai/babysitter --skill axi-protocol

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SKILL.md
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---
name: axi-protocol
description: Expert skill for AMBA AXI protocol implementation and verification in FPGA designs
allowed-tools:
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  - Write
  - Edit
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  - Grep
  - Bash
---

# AXI Protocol Skill

## Overview

Expert skill for AMBA AXI protocol implementation and verification, enabling high-performance interconnect design for FPGA systems.

## Capabilities

- Implement AXI4, AXI4-Lite, and AXI4-Stream interfaces
- Design AXI masters, slaves, and interconnects
- Handle burst transactions (INCR, WRAP, FIXED)
- Implement proper valid/ready handshaking
- Design AXI address decoding and routing
- Create AXI VIP-based verification
- Optimize AXI performance and throughput
- Generate AXI protocol checkers

## Target Processes

- axi-interface-design.js
- ip-core-integration.js
- memory-interface-design.js
- hls-development.js

## Usage Guidelines

### AXI4 Full Features
- Write address channel (AW), Write data channel (W), Write response (B)
- Read address channel (AR), Read data channel (R)
- Burst types: FIXED, INCR, WRAP
- Burst lengths up to 256 beats
- Out-of-order transaction completion

### AXI4-Lite Subset
- Single-beat transactions only
- No burst support
- Simplified for control/status registers
- 32-bit or 64-bit data width

### AXI4-Stream
- Continuous data streaming
- TVALID/TREADY handshake
- TLAST for packet boundaries
- TKEEP/TSTRB for byte enables

### Handshake Rules
- Source must not wait for READY before asserting VALID
- Once VALID asserted, must remain until READY
- Transfer occurs on clock edge when both VALID and READY high
- Deadlock prevention through proper protocol compliance

### Performance Optimization
- Pipeline channels for frequency
- Use write interleaving when supported
- Implement outstanding transaction support
- Size data width for bandwidth requirements

## Dependencies

- ARM AMBA AXI specification knowledge
- Protocol checker integration
- VIP awareness for verification

Overview

This skill provides expert guidance and implementation templates for the AMBA AXI family (AXI4, AXI4-Lite, AXI4-Stream) focused on FPGA designs. It helps design masters, slaves, and interconnects, verify protocol compliance, and optimize throughput for high-performance systems. The skill targets both RTL implementation and VIP-based verification workflows.

How this skill works

The skill inspects AXI interface requirements and produces design patterns for AW/AR/W/R/B channels, stream handshakes, and address decoding/routing. It supplies verification checkers, recommended timing/pipelining strategies, and testbench approaches using VIP to catch protocol violations. It also suggests optimizations like interleaving, outstanding transaction handling, and data-width sizing for bandwidth goals.

When to use it

  • Designing or integrating AXI masters, slaves, or interconnects in an FPGA project
  • Creating memory-mapped interfaces and address-decoding logic for SoC subsystems
  • Verifying AXI protocol compliance with VIPs and protocol checkers
  • Optimizing throughput and latency for high-bandwidth data paths
  • Implementing control/status register access using AXI4-Lite
  • Streaming packet or sample data over AXI4-Stream with TLAST semantics

Best practices

  • Respect VALID/READY handshake rules: assert VALID, hold until READY, and sample on both high
  • Pipeline address and data channels to meet target clock frequency and reduce critical paths
  • Support outstanding transactions and proper ID management when using AXI4 full
  • Keep AXI4-Lite limited to single-beat control paths to simplify logic and verification
  • Use TLAST, TKEEP/TSTRB correctly to mark packet boundaries and byte enables in streams
  • Integrate protocol checkers and VIP early in the verification plan to catch deadlocks and ordering issues

Example use cases

  • Designing a DDR memory controller front-end with AXI4 master interface and burst support
  • Creating an AXI4-Lite register bank for a custom peripheral control block
  • Building an AXI4-Stream video pipeline with TLAST-delimited frames and flow control
  • Verifying interconnect arbitration and address decoding using AXI VIP and protocol checkers

FAQ

Can this skill help with both RTL and verification?

Yes. It covers RTL interface patterns, timing/pipelining recommendations, and VIP-based verification checkers and testbench strategies.

When should I choose AXI4-Lite vs AXI4?

Use AXI4-Lite for simple control/status register access with single-beat transactions. Use AXI4 for memory-mapped data paths that require bursts, outstanding transactions, and higher throughput.