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EDA Tools MCP Server

Provides an integrated MCP server to synthesize, simulate, analyze, and layout Verilog designs with OpenLane and waveform tools.

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Installation
Add the following to your MCP client configuration file.

Configuration

View docs
{
    "mcpServers": {
        "eda_mcp": {
            "command": "node",
            "args": [
                "/absolute/path/to/your/eda-mcp-server/build/index.js"
            ],
            "env": {
                "PATH": "/usr/local/bin:/opt/homebrew/bin:/usr/bin:/bin",
                "HOME": "/your/home/directory"
            }
        }
    }
}

You can extend your AI assistant workflows with this MCP server to access EDA toolchains locally. It connects your AI environment to Verilog synthesis, simulation, ASIC design flows, and waveform analysis so you can perform hardware design tasks through natural language or prompts.

How to use

Use a compatible MCP client (for example Claude Desktop or Cursor IDE) to connect to the MCP server endpoints defined in your local configuration. You will enable two stdio-based MCP connections: one that runs the dockerized socat bridge and another that runs your local MCP server script. Once connected, you can issue requests like synthesize Verilog, run simulations, or execute an RTL-to-GDSII flow and receive results, logs, and generated files through the same interface.

How to install

Prerequisites: you need Node.js and npm, Python, and Docker Desktop installed for OpenLane workflows. Ensure you also have the EDA tools you plan to use (Yosys, Icarus Verilog, GTKWave, OpenLane, KLayout) installed locally if you plan to run full ASIC flows.

Configuration and connections

The MCP server is connected to from MCP clients using two local stdio endpoints. Use the following configuration snippet as the integration blueprint. It enables the Docker-based bridge and a local Node.js MCP server entry.

Examples and usage notes

Verilog synthesis, simulation, and ASIC design workflows are demonstrated through practical examples you can adapt to your designs. You can run synthesis with Yosys, simulate with Icarus Verilog, view waveforms with GTKWave, drive the OpenLane RTL-to-GDSII flow, and inspect layouts with KLayout. The server exposes these capabilities via the MCP interface so your AI assistant can orchestrate toolchains and provide comprehensive results and reports.

Troubleshooting

If the MCP server isn’t detected by your client, verify absolute paths and that Node.js is accessible from your shell. For Docker-related issues, ensure your user is in the docker group and Docker Desktop is running. If a tool isn’t found, confirm it is installed and present in PATH, and verify the MCP configuration is loaded by your client.

Usage references and configuration payloads

{
  "mcpServers": {
    "MCP_DOCKER": {
      "command": "docker",
      "args": [
        "run",
        "-i",
        "--rm",
        "alpine/socat",
        "STDIO",
        "TCP:host.docker.internal:8811"
      ],
      "env": {
        "PATH": "/usr/local/bin:/opt/homebrew/bin:/usr/bin:/bin",
        "HOME": "/your/home/directory"
      }
    },
    "eda-mcp": {
      "command": "node",
      "args": [
        "/absolute/path/to/your/eda-mcp-server/build/index.js"
      ],
      "env": {
        "PATH": "/usr/local/bin:/opt/homebrew/bin:/usr/bin:/bin",
        "HOME": "/your/home/directory"
      }
    }
  }
}

OpenLane/KLayout/EDA tool specifics

This MCP server enables a complete RTL-to-GDSII flow with Docker integration for OpenLane, GDSII layout viewing in KLayout, and waveform analysis via GTKWave. You can also inspect OpenLane reports for timing, area, and power metrics and review design quality indicators.

Environment details

Environment variables shown in the configuration should be included in the MCP server environment blocks as well as your client setup. Use placeholders where values are not specified, and adjust PATHs to match your system layout.

Tools you can access through the MCP server

- Verilog Synthesis with Yosys across generic, ice40, and xilinx targets - Verilog Simulation with Icarus Verilog and automated testbench support - Waveform Viewing with GTKWave for VCD visualization - ASIC Design Flow through OpenLane with Docker integration - Layout Viewing in KLayout for GDSII inspection - Report Analysis from OpenLane for PPA metrics and design quality checks

Available tools

yosys_synthesis

Verilog synthesis with Yosys across generic, ice40, and xilinx targets.

iverilog_sim

Verilog simulation using Icarus Verilog with optional automated testbenches.

gtkwave_view

GTKWave waveform viewer for VCD signal analysis.

openlane_flow

RTL-to-GDSII ASIC design flow using OpenLane with Docker integration.

klayout_view

Open GDSII files in KLayout for physical design inspection.

openlane_reports

Read and analyze OpenLane reports for PPA metrics and design quality.